As computer systems have evolved, the ability to transfer data at high speeds has become increasingly important. One development that has aided that goal is the use high speed serial connections. Such high speed serial links are often implemented as a group of lanes, each lane used to transport a portion of data between two devices. Dividing data into sub-blocks, and sending each sub-block over a different high speed serial lane, allows for scalable high bandwidth.
One context in which high speed serial interfaces can be useful is serving as connections between a master device and a slave configurable device. Examples of such slave configurable devices include Field Programmable Gate Arrays (FPGAs) and Programmable Logic Device (PLDs). Such devices contain hardware capable of being configured in different ways, thus permitting a user to implement different designs without having to undergo a lengthy and expensive process required for designing and fabricating hardware to perform different functions.
Various embodiments of the present disclosure seek to improve upon techniques and mechanisms for configuring an integrated circuit using high speed serial links.